Since the invention of the transistor in the late 1940s, tremendous advances have been made in the field of semiconductors and microelectronics. Today, the dominant semiconductor technology is CMOS—Complimentary Metal-Oxide-Semiconductors. Current CMOS technology allows for the cost-effective fabrication of integrated circuits with over 100 million components—all on a piece of silicon roughly 10 mm on a side. The one billion transistor IC will be commercially available within a few years. The desire for greater functionality and performance at less cost per IC drives several trends.
First, functionality drives IC transistor counts up. Second, the transistors themselves are being reduced in size so as to achieve greater packing density and, very importantly, to improve their performance. As far as performance is concerned, the key parameter for MOSFETs is the channel length. The channel length (L) is a distance that charge carriers travel to pass through the device, and a reduction in this length simultaneously implies higher current drives, reduced parasitic resistances and capacitances and improved high-frequency performance. A common figure-of-merit is the power-delay product, and this generalized measure of transistor performance improves as the cube of the inverse of the channel length (1/L3). This explains the tremendous incentive that IC manufacturers have to reduce the channel length as much as manufacturing capabilities will allow.
For digital applications, MOS transistors behave like switches. When ‘on’, they drive relatively large amounts of current and when turned ‘off’ they are characterized by a certain amount of leakage current. A common CMOS inverter circuit, comprising an NMOS and PMOS device connected in series, dissipates appreciable power only during switching transients. Otherwise, the quiescent power dissipation, or the power dissipated by the CMOS circuit when idle, is a strong function of MOSFET leakage current, and significantly affects the overall circuit power dissipation for most applications.
As channel lengths are reduced, drive current increases, which is beneficial for circuit performance as stated above. However, leakage current increases as well. Leaky transistors contribute to quiescent power dissipation and in extreme cases can affect the transfer of binary information during active operation. Device designers therefore have good reason to keep MOSFET leakage currents low as channel lengths are reduced.
MOS transistor leakage currents are traditionally controlled by introducing controlled amounts of impurities (dopants) into the region between the source and drain electrodes (channel region) of the device, and by tailoring the source/drain lateral and vertical doping distributions. Although these approaches are effective in shoring up the potential barrier internal to the MOS transistor and therefore reducing the leakage current, they can also contribute to degraded drive current and increased parasitic capacitance—the very items that channel length reduction is meant to improve. Furthermore, depending on exactly how in the manufacturing process the channel and tailored source/drain dopants are introduced, the manufacturing cost can be affected significantly.
Another factor affecting the manufacturing cost is process yield. Yield is the ratio of functioning devices to the total number of devices on a fabricated substrate. Process yield is a strong function of the total number of processing steps. For example, if the average yield per process step is 99.5% and a complete CMOS process has 50 processing steps, then the process yield is approximately 90%. The manufacturing cost of a CMOS process is a strong function of the process yield, increasing as process yield decreases. A simple metric that characterizes the manufacturing complexity and therefore cost of a CMOS technology is the total number of mask steps, each of which contains a series of photoresist procedures, mask alignments, lithography exposures, etching steps, cleaning and metrology. Reducing the number of mask steps in a CMOS process directly reduces manufacturing cost by reducing the total number of process steps and additionally by increasing yield. Given traditional MOS transistor design and architecture, and CMOS manufacturing processes, there are only limited solutions to the trade-off between drive current, leakage current, parasitic capacitance and resistance, and manufacturing complexity and cost.
The present invention offers a new relationship between these competing requirements, and makes possible MOS devices and CMOS-based integrated circuits with characteristics that are not achievable with traditional (impurity doped) MOS architectures. The use of metal for the source and drain provides for improvements to device characteristics in terms of reduced parasitic capacitance, reduced statistical variations in these characteristics (especially as the channel length is decreased) and reduced manufacturing cost and complexity.
Doping Profiles
Previous generations of CMOS devices have relied on MOS transistors having laterally uniform, and vertically non-uniform channel doping profiles to control drain-to-source leakage currents. See Yuan Taur, “The Incredible Shrinking Transistor”, IEEE SPECTRUM, pages 25-29 (www.spectrum.ieee.org, ISSN 0018-9235, July 1999). FIG. 1 illustrates an exemplary long-channel conventional MOS device (100) that comprises an impurity doped source (101), an impurity doped drain (102), a conventional MOS type gate stack (103), and a laterally uniform channel doping profile (104) in the substrate to assist in the control of source-to-drain leakage currents. Devices are electrically isolated from each other via a field oxide (105). Such channel dopant profiles are common in devices with channel lengths down to approximately 200 nanometers (nm).
However, as device channel lengths have been reduced into the 100 nm regime the literature teaches that channel doping profiles that are non-uniform in both the lateral and vertical directions are required. Referencing FIG. 2, the exemplary short-channel MOS device (200) has some elements similar to the long-channel MOS device (100). The structure comprises a conventional impurity doped source (201) and drain (202) as well as a conventional MOS gate stack (203) (width<˜100 nm, corresponding to the channel length L). The structure further comprises shallow, impurity doped extensions for the source (208) and drain (209) electrodes which are used in conjunction with drain (206) and source (207) pocket doping as well as conventional channel doping (204) to control source to drain leakage currents. Source and drain electrodes (201) and (202) and their respective extensions (208) and (209) (the combination of all four of which comprise the tailored source/drain doping profile) are all of the same doping polarity (either N-type or P-type) and are of the opposite polarity from the channel (204) and pocket doping elements (206) and (207). Again, a field oxide (205) electrically isolates devices from each other.
Conventional CMOS Circuit
Referencing FIG. 3, a typical CMOS inverter circuit 300 is a P-type MOSFET device 301 and an N-type MOSFET device 302 connected in series fabricated on a lightly doped P-type epitaxial semiconductor layer 331 on a heavily doped semiconductor substrate 330. The source 304,306 and drain 303,305 contacts comprise impurity doped source 304, 306 and drain 303, 305 electrodes, shallow impurity doped source 316, 318 and drain 315, 317 extensions, pocket doping 345, 346 and channel and substrate doping 347, 348. The drain contacts 303,305 of the two devices 301, 302 are connected, the source 304 of the P-type device 301 is connected to a supply voltage Vdd 307, the source 306 of the N-type device 302 is connected to a lower voltage Vss 308, usually ground, and the gates 309, 310 of the two devices 301, 302 have a common connection Vg 311. The PMOS 301 and NMOS 302 devices are isolated by a field oxide 320 and an N-type well implant 321 for the PMOS device, and the N-type well implant 321 is electrically connected via a heavily doped N-type ohmic contact 340 to Vdd 307.
The output voltage Vo 312 at the common drain connection depends on the input voltage at the gate Vg 311. When Vg 311 is high (usually Vdd 307), then the N-type device 302 is “on” and the P-type device 301 is “off”. That is, a channel region 313 of the N-type device 302 conducts while a channel region 314 of the P-type device 301 does not conduct. The result being that the output voltage Vo 312 changes to that of the N-type source 306, or Vss 308. The opposite occurs when Vg 311 is low (usually Vss 308). The N-type device 302 is now “off” and the P-type device 301 “on”, and the output voltage Vo 312 changes to that of the P-type source 304, or Vdd 307. In summary, a high (low) input voltage Vg 311 produces a low (high) output voltage Vo 312, effectively providing an inverting function. One exemplary characteristic of this typical CMOS inverting circuit is that appreciable current only flows during switching of the input voltage Vg 311 from high to low or low to high. Otherwise, when idle, the dominant source of quiescent power dissipation is leakage current.
Schottky Barrier CMOS
In U.S. Pat. No. 5,760,449, Welch discloses a Schottky barrier transistor device system having N-channel and P-channel MOSFETS connected in series, in which source junctions, not drain junctions, of the N- and P-type devices are electrically interconnected, and which uses a mid-gap chromium silicide to form the Schottky barrier source and drain regions of both N- and P-type devices. A mid-gap silicide such as chromium silicide is characterized by a Fermi level that attaches close to the mid band gap for silicon at approximately 0.56 eV. Welch refers to the resulting circuit as a “single device equivalent to CMOS” because the CMOS device is fabricated on a single doping type semiconductor substrate and uses identical metal silicide to form the source and drain regions of both transistors. Both transistors of the device are identical, as compared to conventional CMOS devices in which complimentary opposite-type N- and P-type transistors are used together. Further, Welch teaches that the device demonstrates regenerative inverting switching characteristics. As the device switches, the source voltage changes (not the drain as in a conventional CMOS inverter), thereby increasing the potential difference from gate to source, thereby “regeneratively” or additionally turning the device “on,” until the switching is complete. Welch notes that the mid-gap chromium silicide results in symmetric operating characteristics for the two MOSFET devices, enabling a CMOS-like inverting technology depending on the bias conditions. However, mid-gap suicides also result in unacceptably low drive current and high drain-to-source leakage currents. Further, Welch does not describe the performance of the inverter circuit using short channel MOSFET devices, nor does Welch address the issue of channel or substrate doping to improve the off-state leakage currents of the individual MOSFET devices.
In summary, the prior art does not disclose or teach a Schottky barrier, metal source/drain CMOS device or a fabrication process for the Schottky barrier, metal source/drain CMOS device.
Device Isolation
To fabricate integrated circuits, individual transistor devices must be isolated from one another in order to allow each device to operate independently of other devices in the circuit. Optimal device isolation technologies have high density, reasonable process complexity, high yield, and acceptable parasitic effects. Device isolation divides the semiconductor substrate into regions of two types. A first region has an exposed semiconductor surface and is denoted as an active region—a region in which the transistors are fabricated. A second region comprises a “field oxide” that masks the semiconductor substrate and is denoted as a field region—a region in which no devices are fabricated.
There are many device isolation technologies such as local oxidation of silicon (LOCOS) and shallow trench isolation (STI). Although LOCOS and STI have been optimized for advanced CMOS technologies, they suffer from several integration challenges. Examples of a few LOCOS challenges include stress of the silicon substrate induced during the oxidation process, the white ribbon nitride effect, and the existence of the so-called bird's beak phenomena. Although solutions exist for most of these challenges, they add complexity to the manufacturing process or limit the process flexibility.
Silicide Exclusion Mask Process
Silicides conventionally are provided for across an entire semiconductor substrate. Introduction of silicides may detrimentally affect circuit performance for some applications such as active CMOS pixel arrays (increased photodiode dark current and opaqueness) or analog circuits (degrade signal integrity, aggravate circuit stress, affect threshold voltage offset and junction leakage). A silicide exclusion mask process has been developed in the prior art to selectively mask portions of the semiconductor substrate to prevent silicides from forming in the masked regions. See for example U.S. Pat. No. 6,160,282, in which Merrill discloses a silicide exclusion mask process to improve performance of an active CMOS pixel array and U.S. Pat. No. 5,883,010 in which Merrill discloses a spacer oxide mask process to provide silicide exclusion.
A silicide exclusion mask process typically comprises deposition of a silicide exclusion oxide mask layer, deposition of photoresist, patterning of the photoresist, etching the silicide exclusion oxide mask layer so that regions covered by photoresist and oxide are protected from silicide formation and that regions to be silicided are exposed, stripping the photoresist layer, selectively forming silicide metal layers on silicon surfaces exposed by the silicide exclusion oxide mask pattern, and removing the silicide exclusion oxide mask layer. The silicide exclusion mask technique has not been used to fabricate Schottky barrier CMOS devices and circuits.
Accordingly there is a need in the art for a Schottky barrier CMOS device and fabrication process. There is a further need for a short channel CMOS device with improved performance characteristics that has a simplified, low cost fabrication process.